(1) Field of the Invention
The invention relates to a circuit, and more particularly to a switch circuit for switching clock signals.
(2) Description of the Prior Art
The advance in computer technology, especially in personal computers (PCs), has brought a lot of conveniences to our daily life. Nowadays, a personal computer becomes an inevitable part in our daily living, for a major part of our day-to-day chores such as searching information, gathering news over the network and so on does highly rely on the PC. The personal computer generally includes a motherboard and a plurality of IC chips mounted on the motherboard. For a computer user, quality and stability are the most wanted to a motherboard. Therefore, in order to keep a substantial market share, computer manufacturers have been endeavoring to improve the quality and stability of the motherboard.
On the motherboard, a clock generator is included to provide clock signals for system operation. In early days, clock generators are made by oscillators. However, different frequencies in clock signals are needed for operating the motherboard such that oscillators to generate signals of various frequencies can be seen in distinct areas on the motherboard. In the latest art, these oscillators are integrated into one single chip for providing clock signals with various frequencies. Therefore, upon a request from the system to switch between different clock signals, a 2-to-1 multiplexer 10 (MUX) is introduced to switch clock signals S1 and S2 as shown in FIG. 1.
FIG. 2 shows a clock switching timing diagram according to FIG. 1. It is assumed that frequencies of S1 and S2 are 200 MHz and 250 MHz, respectively. When the system outputted a control signal C1 to switch clock signal (S1 is the original clock signal), the logic level of control signal C1 would change from “low” to “high” at time “t” such that the output clock signal S3 can vary from S1 to S2 simultaneously.
In an ideal situation, as the multiplexer 10 changed the clock signal at time “t”, the frequency of output clock signal S3 (maintained at the frequency of S1 before clock switching at t) is then changed to the frequency of S2 after the clock switching at t. It should be noted that the duty cycle of the output clock signal S3 in the timing period of t can no longer remain at 50% (tp>tn). Thus, a glitch is occurred and error functions are followed at where the circuits adopted the defected clock signal as a reference clock signal. Therefore, the present invention provides a design of signal switching circuit so as to maintain a stable signal output at the moment of signal switching.